Exemplary embodiments of this invention relate to timing detection circuits for detecting timing of a synchronization signal, which may be used in synchronizing processing in, for example, laser-beam printers, digital copiers, facsimile apparatus, or the like. Exemplary embodiments of this invention also relate to apparatus for modulating light beam by utilizing results of timing detection of a synchronizing signal.
In, for example, laser-beam printers, digital copiers, facsimile apparatus, or the like, scanning light beam, which is modulated in accordance with image data, on a photosensitive body produces images. In such apparatus, in order to control the position of the image along a direction of scanning of the light beam, detecting the light beam by means of a light sensor placed at a fixed position generates a synchronizing signal. And the timing of modulating the light beam is set using the synchronizing signal.
Accordingly, for applications of image generation described above, a synchronizing circuit is generally provided. The synchronizing circuit detects the timing of the synchronizing signal and synchronizes the modulation of the light beam with the timing of the synchronizing signal. In the timing detection of the synchronizing signal, in principle, a video clock and the synchronizing signal is compared and the timing of the synchronizing signal with respect to the video clock is detected. Then, in accordance with the result of timing detection, one of following procedures (synchronizing procedures) is performed.
a. An adjusted video clock having a timing adjusted in accordance with the result of timing detection is generated (or, a plurality of video clocks is generated and one of the clocks having a suitable timing is selected from among them), and the light beam is modulated with reference to the adjusted (or selected) video clock; or
b. The same video clock (or a reference clock) is used regardless of the result of timing detection, but the timing of modulating the light beam with respect to the reference clock is adjusted in accordance with the result of timing detection.
However, it is only possible to detect the timing of the synchronizing signal with an accuracy of a cycle of the video clock by comparing the video clock and a synchronizing signal as they are. Accordingly, as described in Patent Document 1 (Japanese Laid-open Patent Hei 04-249971), for example, following improved techniques, which aim to improve the accuracy of timing detection of a synchronizing signal, are proposed in order to improve the image quality.
1. A high-frequency clock having a frequency of n-times (n is an integer equal to or larger than 2) the video clock is generated, and the high-frequency clock is compared with a synchronizing signal
2. Multiphase clocks having the same frequency as the video clock and m (m is an integer equal to or larger than 2) mutually different phases are generated, and each of the multiphase clocks are compared with a synchronizing signal.
Further, for example, Patent Document 2 (Japanese Laid-open Patent Hei 11-245447) proposes a following procedure. That is, as a first-stage timing detection, a high-frequency clock is compared with a synchronizing signal and a video clock is generated in accordance with a result of the first-stage timing detection. Moreover, as a second-stage timing detection, generated video clock is compared with the synchronizing signal and also with a plurality of delayed synchronizing signals, which are successively delayed by a fixed period. And a further timing adjustment of the clock signal by generating a plurality of video clocks and selecting one of them having a proper timing is performed in accordance with a result of the second-stage timing detection.
The first technique described above may achieve n-time improvement of the accuracy of timing detection of the synchronizing signal by an n-time increase of the frequency of the high-frequency clock. However, increasing the frequency of the high-frequency clock increases the power consumption and instability of the semiconductor integrated circuit that constitutes the synchronizing circuit. Accordingly, improvement of the accuracy by using this technique has a limitation.
The second technique described above may improve the accuracy of timing detection of the synchronizing signal by generating a large number of multiphase clocks with small phase differences between them and by comparing them with the synchronizing signal. However, the size of the circuitry increases because it is necessary to compare each of the multiphase clocks with the synchronizing signal. The increase of the size of circuitry also results in the increase of power consumption.
In Patent Document 2, as a first-stage timing adjustment, a first-stage timing detection by comparing a high-frequency clock with a synchronizing signal is performed and a video clock is generated. Then, a further timing adjustment in accordance with a second-stage timing detection by comparing the generated video clock with the synchronizing signal and the successively delayed synchronizing signals is performed. Accordingly, it might be possible to improve the accuracy of timing detection without excessively increasing the frequency of the clock or the size of the circuitry. However, there is a difficulty in performing the synchronization by combining the results of the first- and the second-stage timing detections.
Particularly, in Patent Document 2, according to the procedure “a” described above, a video clock to which a timing adjustment is performed is generated in accordance with results of timing detections. However, no technique is disclosed to enable the procedure “b” described above to adjust a timing of modulation with respect to a reference clock in accordance with results of timing detections.